In a semiconductor device, there is an ASV (adaptive supply voltage) technology in which a power supply voltage is changed in accordance with process conditions (for example, element characteristics of transistors or the like formed in a chip). The ASV technology is applied, and for example, the power supply voltage applied to a semiconductor device (chip) whose transistor is finished to be a fast side (a transistor which is finished to have a low threshold value) is lowered to thereby lower an operating power by suppressing a leak current, then it becomes possible to suppress power consumption equal to or lower than a semiconductor device whose transistor is finished to be a slow side (a transistor which is finished to have a high threshold value).
In a semiconductor device including an SRAM macro, there is one including a read assist function enabling stability at a data read-out time by lowering a signal level which is in high level at a word line in a plurality of stages (for example, refer to Patent Documents 1 to 3). As for an SRAM cell transistor in a semiconductor device, an art in which the element characteristics thereof are measured by a ring oscillator formed in the semiconductor device has been proposed (for example, refer to Patent Documents 4, 5). An art measuring AC characteristics of a memory macro in a semiconductor device has been proposed (for example, refer to Patent Document 6).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2008-262637
[Patent Document 2] Japanese Laid-open Patent Publication No. 2011-54255
[Patent Document 3] Japanese Laid-open Patent Publication No. 2010-282704
[Patent Document 4] Japanese Laid-open Patent Publication No. 2010-109115
[Patent Document 5] Japanese Laid-open Patent Publication No. 2014-10874
[Patent Document 6] International Publication Pamphlet No. WO 2005/008677
When the ASV technology is applied for a semiconductor device including a plurality of kinds of transistors, the power supply voltage is determined according to a transistor which is at the slowest side in the semiconductor device so that an operating specification is satisfied by all of circuits. For example, when there is an SRAM cell transistor in the semiconductor device, the transistor of the SRAM cell is finished to be fast, and one or more transistors of other peripheral circuits are finished to be slow, high power supply voltage is supplied according to the transistors of the peripheral circuits, and the power supply voltage does not become one which is suited to the SRAM cell transistor.
In this case, a voltage which is higher than a supposed power supply voltage when the transistor is finished to be fast is applied to the SRAM cell transistor, and therefore, there is allowance in read characteristics and write characteristics, but a read-out speed becomes excessively fast. Conventionally, it has been necessary to set a specification of an SRAM macro with a large margin considering the situation as stated above and to perform a timing verification of the semiconductor device.